Job brief: FPGA/ASIC Design Engineer (Silicon Engineering)
SpaceX · Irvine, CA · facts as of 2026-11-07. Anyone can open this page; no account needed.
Is it still open? · Checked by JoRoute
Still listed. JoRoute saw it on SpaceX's own job board 7 hours ago; the employer first posted it on 2026-09-30.
What JoRoute checked · Checked by JoRoute
- Listed on SpaceX's own job board. JoRoute does not take listings from job ads or recruiters.
- First seen by JoRoute 2026-11-04 (3 days ago); last confirmed on the board 2026-11-06.
- The apply link opens boards.greenhouse.io, the address SpaceX's board gives for this job.
- No other listing with this title and place on this board in the last 90 days.
- No layoff notices (WARN) under this name in the state files JoRoute reads.
What the listing says · Employer's own words, not checked
- Pay: $125,000 to $195,000 a year
- Job type: Not stated
- Where: Irvine, CA · Redmond, WA
- Posted: 2026-09-30
What the job asks · Employer's own words, not checked
Level: Entry level. The posting asks for 1+ years of experience.
Must have
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
- Master’s in Electrical/Computer Engineering or related field
- Government export regulations, applicant must be a (i) U.S.
- § 1158, or be eligible to obtain the required authorizations from the U.S.
Conditions
- Ability to work extended hours or weekends as needed for mission critical deadlines
- You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year.
- employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/…
Main duties
- Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog
- Optimize designs for power, performance and area
- Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture,…
- Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
- Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communica…
Lines copied from the posting, not rewritten. "Preferred" or "nice to have" items are not listed as must-haves.
How it compares · Compared by JoRoute from listings
- Typical listed pay for engineer jobs in Washington: $157k a year (843 listings, 40 employers). This listing pays about the same.
- Across SpaceX's 2,895 open listings, 60% of those with a posting date were first posted more than 60 days ago. How SpaceX hires
What nobody outside the employer knows · Not known
- Whether the role is already filled or on hold: employers often leave listings up.
- How many people applied, and who reads the applications.
- Where in the published range an offer would land.
Ask before you apply
- Which of the listed places is this role based in?
- What are the interview steps, and when should I expect to hear back?
Next steps
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A summary of facts and listings, not a verdict that this job or employer is safe. JoRoute is not affiliated with SpaceX. How JoRoute checks listings · Original posting

