Job brief: Physical Design and Verification Engineer

What JoRoute checked · Checked by JoRoute

• Listed on Neuralink's own job board. JoRoute does not take listings from job ads or recruiters.
• First seen by JoRoute 2026-11-06 (2 days ago); last confirmed on the board 2026-11-08.
• The apply link opens boards.greenhouse.io, the address Neuralink's board gives for this job.
• No other listing with this title and place on this board in the last 90 days.
• No layoff notices (WARN) under this name in the state files JoRoute reads.

What the listing says · Employer's own words, not checked

• Pay: $131,000 to $265,000 a year
• Job type: Not stated
• Where: South San Francisco, California, United States · Fremont - Campus
• Posted: 2026-11-05

What the job asks · Employer's own words, not checked

Level: Senior. The posting asks for 5+ years of experience.

Conditions

• We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products.
• You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to st…
• Synthesis: Drive logic synthesis (constraints, DFT insertion, physical-aware synthesis), QoR analysis, and RTL-to-gate correlation.
• Signoff: Static timing analysis (STA) across all corners/modes, physical verification (DRC/LVS/DFM), EM/IR (static and dynamic), and formal netlist equivalence.

Main duties

• Hierarchical Physical Design
• Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy.
• Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs.
• Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation.
• Manage die-to-die partitioning for 3D stacks – assign logic to tiers, plan hybrid-bond / µbump / TSV interfaces, and align inter-die floorplans.

Lines copied from the posting, not rewritten. "Preferred" or "nice to have" items are not listed as must-haves.

How it compares · Compared by JoRoute from listings

• Typical listed pay for engineer jobs in South San Francisco, CA: $189k a year (27 listings, 2 employers). This listing pays about the same.
• Across Neuralink's 80 open listings, 78% of those with a posting date were first posted more than 60 days ago. How Neuralink hires

What nobody outside the employer knows · Not known

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• How many people applied, and who reads the applications.
• Where in the published range an offer would land.

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